Most semiconductor chip products are treated in a typical testing board system as shown in FIG. 1 or FIG. 2, in which a drive channel 2 of a test driver is connected to a drive pin UB of a semiconductor chip (IC1, IC2, IC3, or IC4) to be tested. An input/output channel 3 of the test driver is connected to an input/output pin DQ0. It uses a one-by-one testing scheme where one channel of the test driver is assigned to one pin of the semiconductor chip to be tested.
Such a one-by-one testing scheme is not advantageous to a multi-chip package (MCP), e.g., 1 or 4, mounted with a multiplicity of semiconductor chips in a common assembly process. As it is usual that the MCP operate with different stations and functions in a given system, a test driver is equipped with a multiplicity of drive channels and input/output channels corresponding to drive pins and input/output pins of the semiconductor chips. Moreover, it is necessary to perform a number of test steps according to the number of semiconductor chips mounted on the MCP module, as well as additional test boards. Testing efficiency limits result increasing test complexity and distribution cost. This, in turn, deteriorates test productivity.